In recent years, monolithic integration of a gate driver has been developed for the purpose of cost reduction. In the monolithic integration, the gate driver is formed from amorphous silicon on a liquid crystal panel. The term “monolithic gate driver” is also associated with the terms such as “gate driver-free”, “built-in gate driver in panel”, and “gate in panel”. For example, Patent Literature 1 discloses shift registers of monolithic gate drivers.
FIG. 11 shows circuit configuration of each shift register stage disclosed in Patent Literature 1.
The following describes essential structure and operations of this circuit. FIG. 11 shows the structure of an n-th stage of shift register stages cascaded with each other. To an input terminal 12, a gate output from a preceding stage is supplied. This supply causes an output transistor 16 to be turned ON through a drain of a transistor 18. A bootstrap capacitor 30 is connected between a gate and a source of the output transistor 16. When a clock signal C1 in High level is supplied to the output transistor 16 from its drain side during ON-state of the output transistor 16, a gate potential of the output transistor 16 sharply increases to a level greater than power source voltage due to capacitive coupling between the gate and source of the output transistor 16 through the bootstrap capacitor 30. This substantially decreases a resistance between the source and drain of the output transistor 16. Then, the clock signal C1 in High level is outputted to a gate bus line 118, and this gate output is supplied to an input of a subsequent stage.
FIG. 12 shows a plan view of elements used when such a bootstrap capacitor is built into a display panel.
A bootstrap capacitor 101b shown in FIG. 12, as part of a TFT 101, is connected to a TFT body section 101a. In a case where a display panel is made from amorphous silicon or the like material with lower mobility, it is a widespread practice that the TFTs monolithically built into the display panel are patterned to have a much larger channel width than standard for decrease in resistance between a source and drain of the TFT body section 101a. Therefore, the TFT body section 101a shown in FIG. 11 secures a large channel width, with such an arrangement that comb-shaped source electrode 102 and drain electrode 103 are arranged to be mutually opposed in such a manner that the source electrode 102 and the drain electrode 103 are engaged with each other. Under a region of the engagement between the source electrode 102 and the drain electrode 103, a gate electrode 104 is provided. The bootstrap capacitor 101b is formed such that a first capacitor electrode 102a led out from the source electrode 102 of the TFT body section 101a and a second capacitor electrode 104a led out from the gate electrode 104 of the TFT body section 101a are arranged to be stacked and mutually opposed across a gate dielectric layer therebetween.
In addition, the first capacitor electrode 102a is connected to an output OUT of a shift register stage, and the output OUT is connected to a gate bus line GL via a contact hole 105.
FIG. 13 shows a cross-sectional view taken along the line X-X′ in FIG. 12.
As shown in the cross-sectional view of FIG. 13, the arrangement in FIG. 13 is such that: a gate metal GM, a gate dielectric layer 106, an i layer 107 formed from Si, an n+ layer 108 formed from Si, a source metal SM, and a passivation layer 109 are stacked on a glass substrate 100 in this order. The gate electrode 104, the second capacitor electrode 104a, and the gate bus line GL are all formed from the gate metal GM that has been formed in a concurrent manufacturing process. The source electrode 102, the drain electrode 103, and the first capacitor electrode 102a are all formed from the source metal SM that has been formed in the concurrent manufacturing process. The i layer 107 is a layer that serves as a channel forming region in the TFT body section 101a. The n+ layer 108 is provided as a source/drain contact layer between the i layer 107 and the source electrode 102 and between the i layer 107 and the drain electrode 103.
The above-described transistor including the bootstrap capacitor is also disclosed in Patent Literature 2, etc.